Field of Invention
This invention relates to a method and in particular, to a sequence of fabrication steps for constructing semiconductor lasers, and in particular, vertical cavity surface emitting lasers (VCSELs) and arrays of VCSELs, exhibiting long term stability and reliability.
Background Art
The fabrication processes for making VCSELs involve a series of steps as shown in a process flow diagram shown in FIG. 1. A VCSEL or VCSEL arrays (synonymously referred as VCSEL devices hereinafter) are grown on a semiconductor substrate and in general, includes steps of one or more layers of epitaxial crystal growth, growth or deposition of different materials to facilitate etching of layers, lithography, metallization, polishing, bonding, dicing and cutting, etc. While each process and its implementation is optimized for better device performance, design, engineering and execution of these processes has a direct impact on device performance including stability and long term reliability. The number of steps and in particular, the number of epitaxial layer growth steps for constructing VCSEL device is much larger than for other semiconductor optical devices. Therefore, designing a process applicable for high volume and large area wafers in manufacturing environment is particularly challenging due to stress arising from one or more process steps including growth of large number of epitaxial layers.
Bulk single crystal semiconductor is grown using high precision processes and are cut into discs and polished to obtain high quality wafer surfaces as the starting substrate material for growing one or more epitaxial layers to construct VCSEL devices. One of many methods such as Metal-Organic Chemical Vapor deposition (MOCVD) and/or Molecular beam Epitaxy (MBE) are well known in the art to grow epitaxial layers with precise composition and thickness control. Such epitaxial layers are used to construct reflectors including Distributed Bragg Reflectors (DBR) and dielectric mirrors as well as the active gain region to form a laser cavity, aperture layer(s) for current confinement, etch stop layer and electrical contact layers. Typically, a large number of layers of desired composition are grown to achieve a structure having a complex optical profile of the VCSEL device that different applications of such VCSEL devices may need. For example, in one application described in the U.S. Pat. No. 8,411,722, epitaxial layers are grown with a composition and thickness to impart a wide reflectivity profile to at least one reflector for stable operation.
The number of layers required, and complexity of composition and thickness requirements are described in many prior art patent and non-patent literature publications. U.S. Pat. Nos. 5,594,751, 6,898,215, 7,286584, 8,451875, United States Patent Application Publication No. 2005/0019973 and European Patent Application Publication No. EP0905835 are cited here to highlight the requirements of epitaxial growth layers to construct a VCSEL device. Most of the structures described in the above cited literature are grown on III-V semiconductor substrate. Since a large number of thin layers having slightly different lattice properties are grown successively, one common aspect is that lattice strain is induced in the active layer during the process. The strain in the active region may generate defects and/or dislocations in the resulting structure which affect stable operation and reliability.
A common way to improve stability and reliability in most VCSEL device structure is to deliberately introduce a strain of opposite kind, in one or more layer (strain layer) in the stack of epitaxial layers to compensate for the overall lattice strain, which require precise control on composition and thickness. The strain layer may be placed at one or several levels in the entire stack of the plurality of epitaxial layers (most common approach) or at a specific level for example, next to an oxidation layer as described in the United States Patent Application Publication No. 20050184303. Different approaches to mitigate strain in the active layer may be followed when VCSEL devices are constructed on Silicon (Si) or other substrates depending upon the emission wavelength. For example, in the United States Patent Application Publication No. 2013/0270575, a VCSEL device constructed using Gallium Nitride (GaN) on a Si substrate, is described where active layer strain is mitigated using one or more Silicon Nitride (SiNx) interlayers placed at one or more specific positions in a stack.
The number, complex compositions and precision control on composition and thickness of the epitaxial layers involved in the construction of VCSEL devices is much higher than for other typical semiconductor optical devices. As a result there is high degree of variations in the crystal lattice dimensions between adjacent or overlying layers. These structural modifications which are critical for intended device operation, results in inducing strain in the epitaxial layers and also between the epitaxial layers and the substrate wafer. Thus significant bowing and/or warping of the wafer (including the epitaxial layers) may occur, which not only induces strain in the device but lack of flatness is particularly detrimental for some critical processing steps for example lithography, on a large area and/or thin substrates used in a manufacturing environment, and therefore impacts yield.
Introducing a specially designed strain compensation layer is often used in growing epitaxial layers on dissimilar substrates for example growing III-V or III-N (GaN) optical layer on a Si substrate. In the United States Patent Application Publication No. 20130099357 a method to grow III-N optical layer on a Si substrate is described. More specifically, a rare earth oxide (REO) layer is first grown on the Si substrate as a strain compensation layer prior to growing of the III-N layer over the strain compensation layer. The resulting combination reduces bow in the III-N material. Notably, the strain compensation layer and the III-N layer are deposited in tandem on the same side of the substrate. In a U.S. Pat. No. 8,093,143, a stress compensating layer comprising of a constant composition of SiGe of a desired thickness is grown on the back side of a Si wafer to change the growth process of a Si—Ge layer grown on the front side of the Si wafer. It was observed that the defects on the film as well as bowing were reduced. However, the process introduced other defects that compromise device performance.
While strain layers are incorporated in the epitaxial layer structure for reducing defects in the gain region, in most prior art designs of VCSEL devices cited earlier, mitigating bow and/or warp arising from the epitaxial layer structure has never been considered to be an important process step, more so when epitaxial layers and the substrate are from the same family of compounds (InGaAs/GaAs,GaAlAs on GaAs substrate, for example), and/or for small area wafers (3″ diameter or less). Furthermore, incorporating an appropriately designed strain compensation layer on the substrate on a surface opposite to the epitaxial layer structure is not considered or incorporated in the design of a fabrication process before.
Another critical fabrication step in the VCSEL construction is forming current and optical mode confining apertures for ensuring high optical gain and desired optical mode characteristics. While the optical aperture may be created during a metallization step, the current confining aperture is formed by proton implantation as described for example in U.S. Pat. No. 7,346,090. More recently, oxidizing a suitably placed epitaxial layer of a specific composition at one or more positions within the epitaxial layers stack has emerged as a more preferred option to create the current confinement aperture as described in the U.S. Pat. No. 5,594,751. In this particular patent it is described that the aperture size should preferably be smaller than the beam waist diameter such that a single oxide aperture suffices for current and optical mode confinement.
More detailed account of the advantages of oxide aperture is provided in non-patent literature publication in a report published by Finisar entitled “Reliability of Various Size Oxide Aperture VCSELs”, first published in Proceedings of 52nd Electronic Component and Technology Conference 2002, vol. 52, pp. 540-550 (doi: 10.1109/ECTC.2002.1008148). One important drawback of oxide apertures arises from the volume of oxide present in the VCSEL device that may introduce stress and affect reliability. In the U.S. Pat. No. 6,949,473 it is described that for low current operation of the VCSEL device the oxide aperture diameter must be small as compared to the mesa diameter. However, a large volume of oxide grown to reduce the aperture diameter to a required size as compared to the mesa diameter may result in significant difference in thermal expansion rates of the VCSEL epitaxial layers and the oxide region, causing stress and thereby affecting reliability.
Current confinement and confinement of a preferred optical mode is achieved by a two aperture design. In the European Application Publication No. EP1496583, a first oxide ring in the epitaxial layer stack is used for current confinement whereas a second oxide ring around the mesa structure of the VCSEL device is used to cut down transverse optical modes thereby facilitating single mode operation to improve reliability. In a different design described in the United States Application Publication No. 2013/0034117, two apertures, one oxide aperture to confine current and a second oxide aperture to confine a preferred optical mode are utilized. In another approach described in a U.S. Pat. No. 8,355,423 a non-circular current confinement aperture is used for promoting higher order lateral modes. One common factor in this approach is to have a predetermined ratio between the sizes of the two apertures as has also been described in the European Patent Application Publication No. EP1496583.
Temperature and thermal cycling during the oxidation process is also responsible for introducing strain in the wafer and in the epitaxial layers which in turn may contribute to the bowing and/or warping of the substrate wafer. Therefore it is important to design oxidation processes that are at lower temperature and follow slow thermal cycling to avoid stress in the wafer. Current confinement aperture constructed by oxidation has a second detrimental aspect. Besides the epitaxial growth and oxidation steps, there are several other process steps in VCSEL device construction that may strain/stress the device structure. Operation of VCSEL devices particularly at high power levels creates significant heat in the device.
Therefore optimum operation requires VCSELs to be designed with high thermal conductivity to dissipate heat which would otherwise limit performance and output power of the VCSEL. A preferred mounting configuration for high power operation of VCSEL devices is in the bottom emission mode where VCSEL device is bonded to a high thermal conductivity submount with the substrate distal to the submount. In this configuration the output beam from the VCSEL devices traverses through the substrate. Therefore, operation of the VCSEL device is restricted to wavelength emissions that are not absorbed in the substrate. In one mode the substrate is either thinned to suitable thickness or completely removed by polishing and/or etching which may introduce further strain if wafer is not handled properly and in particular has bowing and/or warping during the thinning operation.
In a later processing step electrical contacts to the VCSEL device are made. Most often one or more lithography steps are performed to etch mesas, define the areas to be selectively metallized to define the contact areas, and so forth. The lithography step may precede or follow the metallization step according to the process design. A flat wafer surface free of bowing and/or warping is necessary for accurate geometry of the mesas and metallization features to be defined on the wafer. Flatness of the wafer, particularly for a large area wafer in a manufacturing environment is absolutely necessary for better yield. Typical metallization deposition is performed at elevated temperature to ensure good adhesion of the metal layer to the semiconductor material of the VCSEL device to realize low electrical resistance of the metallization contact. However, high temperature process can introduce defects into the device and potentially degrade the properties of the device structure fabricated in earlier process steps. Therefore, a low temperature metallization process will be a preferred choice for making electrical contacts to the VCSEL device without compromising stable and reliable operation over long time.
Another process step that may introduce stress in the epitaxial layers of VCSEL device is the final step of dicing the wafer into individual chips. The dicing saw or even the dicing scribe has the potential to create crystal defects which can then propagate into the epitaxial region of the VCSEL device or arrays of devices. These defects may affect one or more properties of the VCSEL epitaxial layers thereby reducing inherent gain of the device causing optical loss and impacting long term stability and reliability.
Although many process steps for constructing of VCSEL devices are well known, and have been optimized for smaller size wafers and for particular material systems, applying same process steps to large size wafers and/or to thin wafers is particularly challenging because bowing and/or warping of wafers may be sufficiently large to affect the flatness of the wafer in subsequent post epitaxial layer growth processing steps, for example, while performing critical alignment steps such as lithography, substrate thinning/removal, metallization, etc. In addition, wafer bowing and/or warping is particularly detrimental in bonding the finished VCSEL device to a submount including a thermal submount or a printed circuit board with or without a region for efficient heat dissipation, which affects the performance of high power VCSEL devices in particular. Efficient heat dissipation is only possible if the VCSEL device is positioned flat and in close contact with the submount. In case of a thin wafer the bowing may even cause breakage thereby resulting in poor yield.
Standard prior art VCSEL device processing methods are quite advanced, but still do not address or provide a solution to this important issue of bowing and/or warping which poses challenges in adapting standard VCSEL device processing on a large area wafer particularly for large scale manufacturing environment. There are many steps that may introduce stress in the structure which degrades performance and ultimately compromises reliability and leads to device failure. Therefore there is a need to design a fabrication process and apply the process steps in a preferred order to mitigate or minimize the effects of wafer bowing and/or warping. One objective of this invention is to minimize stress on VCSEL device wafer thereby improving long term stability and reliability. In this invention a number of process steps are provided that when applied in a prescribed sequence has demonstrated to reduce overall stress and improve long term stability and reliability. VCSEL device fabricated in accordance with the process design of this invention on a large area wafer and operated at optical power levels exceeding 1 Watt (W) exhibit improvement in reliable performance by a factor of 20 or more.